The present invention relates to a power-on reset circuit for monitoring a variation of a power source voltage applied to a digital circuit or the like.
Circuit elements, such as transistors, forming a digital circuit or the like would improperly operate when the power source voltage applied thereto drops below a preset value. Such a drop causes many serious problems. For example, incorrect data is stored, the stored data is destroyed, and an error signal is applied to related circuits.
A power-on reset circuit has been employed in order to avoid the situations involving such problems. The power-on reset circuit operates as follows. The power-on reset circuit continuously monitors a power source voltage. When a power source voltage exceeds a predetermined value, the power-on reset circuit allows a digital circuit to start operating. When the power source voltage drops to below the predetermined value, the power-on reset circuit immediately quits the operation of the digital circuit, and moves the necessary data to safe places.
FIG. 7 is a circuit diagram showing a conventional power-on reset circuit. The conventional power-on reset circuit shown in FIG. 7 includes a resistor 1, a capacitor 2, an invertor 3, a node 4, an output terminal 5, a power voltage terminal 13, a substrate 14, a power voltage V.sub.DD, and a substrate voltage V.sub.SS. For ease of explanation, V.sub.SS is set at O V, V.sub.SS =0 V in the following description of the invention.
The node 4 is a connection point between a line connecting the resistor 1 to the capacitor 2, and a line connecting to the input of the invertor 3. The resistor 1 and the capacitor 2 constitute a time constant circuit.
FIG. 8 is a graph showing an operation of the power-on reset circuit illustrated in FIG. 7. In the graph, the abscissa represents time T, and the ordinate voltage V. The power voltage V.sub.DD, voltage V4 at the node 4, and voltage V5 as an output voltage of the invertor 3, vary as shown in FIG. 8. V.sub.IV represents an input threshold voltage of the invertor 3. A logical state of the output of the invertor 3 is inverted at the threshold value V.sub.IV.
When the power voltage V.sub.DD is applied to the invertor 3, the voltage V4 rises along a curve defined by a time constant constituted by the resistor 1 and the capacitor 2. The output voltage V5 of the invertor 3 is kept in logical high before time point t1 at which the voltage V4 reaches the threshold voltage V.sub.IV. When the voltage V4 reaches the threshold voltage V.sub.IV, the output voltage is inverted to be low in logical state. The high-to-low change of the output voltage of the invertor 3 indicates that the power source voltage has risen up to a predetermined value, and hence the digital circuit will operate normally.
Unexamined Japanese Patent Application (OPI) No. Sho. 56-68027, for example is enumerated for articles describing the conventional power-on reset circuit.
The power-on reset circuit as mentioned above suffers from the problems as stated in the following. The first problem is that a large space is required for constructing the time constant circuit. The second problem is that it takes a relatively long time to detect a change of the power voltage after it actually changes, and further that an interruption (simultaneous stoppage) cannot be detected if occurring in the power source. The third problem is that it is very difficult to obtain an optimum time constant characteristic of the time constant circuit. The reason for the third problem is that the time constant circuit is constituted by the resistor and the capacitor and hence its characteristic is influenced by the variation in the values of those components.
The first and second problems will be described more specifically, however, no further description of the third problem is given because it is believed that no particular description is required about the third problem.
With respect to the first problem, the digital circuit designed such that it starts to operate in response to an instruction by the output signal of the power-on reset circuit is generally fabricated into an integrated circuit. For this reason, it is desirable to fabricate also the power-on reset circuit as an integrated circuit on a semiconductor substrate. The resistor and capacitor, when fabricated, requires large areas than the transistors.
Concerning the second problem, the voltage V4 takes a relatively long time until it reaches the threshold voltage value of the invertor 3. Therefore, the power-on reset circuit sometimes fails to detect an interruption, if it occurs.
For example, now assuming that the power voltage is interrupted at time point t2 and restored to the normal voltage at time point t3 as illustrated in FIG. 8, in this case, the voltage V4 begins to drop at time point t2 according to the time constant. The power voltage restores to the normal voltage before it drops to reach the threshold voltage V.sub.IV of the invertor 3, so that it increases again according to the time constant. Accordingly, the output voltage of the invertor 3 remains unchanged. Thus, the power-on reset circuit fails to detect the variation of the power voltage due to the interruption.